1.Control signals and clock:
a.clk32: 32 MHz TTL clock from the Mother Board as main clock. The clock can be from oscillator on the DB.
b.clk3225: 32.25 MHz TTL clock derived after converting ECL signals.
c.mstinitn: The Master init signal to synchronize the cards with rest of the systems.
d.mctrl: The jumper selectable signal is for master control and puts the whole card into test mode. The output data is some predefined test signal.
e.nonoff[0..1]: This signal is for synchronizing with noise generator switching on and off from each antenna, to be used by total power detection for bank switching while accumulation of power.
f.wsync[0..1]: This signal is synchronizing with the walsh sequence for a given antenna.
g.dbsync: This signal is meant for blanking the data at external request.
h.d1oe: Output enable for device one, jumper selectable. To be used for debugging purposes.
i.d2oe: Output for device two, jumper selectable. To be used for debugging purposes.
2.Data input and output:
a.din[1..4]*[0..7]: Input data (8 bits per polarization).
b.dop[1..4]*[0..7]: Output data (8 bits per polarization, only 5 to be used).
3.PROM and RAM signals with their control signals:
a.pop[1..4]*[0..7]: PROM outputs
b.pad[1..4]*[0..11]: PROM addresses
c.pesn: Control signal for PROM.
d.pinitn: Control signal for PROM.
e.r[1..4]D[0..7]: RAM data bits, for delaying the signal and for re-circulation of data for filtering.
f.r[1..4]A[0..14]: Address bits for RAM, these are generated by NCO and hence used for de-sampling, and delaying the signal.
g.r[1..4]CSn: Control signal for RAM.
h.r[1..4]WEn: Control signal for RAM.
i.r[1..4]OEn: Control signal for RAM.
4.Bus communication signals:
a.dio[0..15]: The data bus. The address of card is given by dio[0..7] and the data meant for the card is given by dio[8..15].
b.ddir: Gives the direction of transfer for data.
c.iodclk: The clock for data latching.
d.hshkout: Handshake out signal for informing the host communicator about the completion of data transfer.
e.hshkin: Handshake in signal for indicating the appearance of valid data on, data and address on the bus.
f.ioclkdir: Signal to indicate the direction of clock.
5.Spare signals:
a.c1sp[0..31]: Spare signals from connector to device (planned to be used for other applications of the card).
b.c2sp[0..26]: Spare signals from connector to device (planned to be used for other applications of the card).
6.Signals between the devices:
a.1d2[0..11]: For transfer of control and other information between the devices.
7.Power and ground signals:
a.VCC: Main power input (+5V) to the card.
b.GND: Ground for card.
c.VEE: Power input (-5V) to the card.
d.d1VCC: 3.3V to the card for FPGA d1 and associated components.
e.d1VCCIO: 3.3V to the card for FPGA d1 and associated components.
f.d1VCCINT: 3.3V to the card for FPGA d1 and associated components.
g.d1GND: Ground signal for FPGA d1.
h.d2VCC: 3.3V to the card for FPGA d2 and associated components.
i.d2VCCIO: 3.3V to the card for FPGA d2 and associated components.
j.d2VCCINT: 3.3V to the card for FPGA d2 and associated components.
k.d2GND: Ground signal for FPGA d2.